The present invention relates to a memory system, and more particularly, the present invention relates to a memory system that detects and corrects read errors.
Data that has become damaged due to various causes may be efficiently recovered by error detecting and correcting technologies. For example, data may be damaged while residing in memory and/or while being transferred from a source to a destination through a data transfer channel.
Various methods have been proposed to detect and correct damaged data. Well-known error detecting techniques include Read-Solomon (RS) code, Hamming code, Bose-Chaudhuri-Hocquenghem (BCH) code. Cyclic Redundancy Code (CRC) code, and the like. It may be possible to detect and correct damaged data using these codes.
In electronic devices using non-volatile memory devices, data may be stored in the non-volatile memory device (e.g., a flash memory device) together with a value called Error Correcting Code (ECC) (hereinafter, referred to as ECC data). As is well known in the Art, ECC data may be used to correct an error during a read operation from a flash memory device. However, the ability to correct such errors may be limited by the number of erroneous bits that are capable of being simultaneously corrected using the particular type of ECC data. A bit error that is detected during a read operation may be corrected via an error detecting and correcting code without necessitating the use of a separate data repairing process, such as a block replacement process.
FIG. 1 is a block diagram showing a conventional flash memory device, and FIG. 2 is a timing diagram illustrating a read operation of the flash memory device of FIG. 1.
A conventional flash memory device may include a memory cell array, which has a plurality of memory blocks. Only one memory block BLK0 is illustrated in FIG. 1. The memory block BLK0 may include strings (or, referred to as a NAND string) that are connected to bit lines, respectively. Each of the strings has a string select transistor SST, a ground select transistor GST, and memory cells (or memory cell transistors) MC0-MCn−1 connected in series between the select transistors SST and GST.
Gates of the select transistors SST and GST are connected to string and ground select lines SSL and GSL, respectively. Control gates of memory cell transistors MC0-MCn−1 are connected to corresponding word lines WL0-WLn−1, respectively. Bit lines BL0 and BL1 are connected with corresponding page buffers PB, respectively.
For a read operation, as illustrated in FIG. 2, a selected word line (e.g., WL0) is driven with a voltage of 0V, and respective un selected word lines (e.g., WL1˜WLn−1) are driven with a read voltage Vread. At this time, string and ground select lines are supplied with the read voltage Vread, respectively. Page buffers PB apply sensing current to corresponding bit lines BL0 and BL1.
Voltages on the bit lines BL0 and BL1 may be determined according to cell states of memory cells that are connected with the selected word line. For example, if a memory connected with the selected word line is an ON cell, a voltage on a bit line may be lowered to a ground voltage. On the other hand, if a memory connected with the selected word line is an OFF cell, a voltage on a bit line may be increased to a power supply voltage. Afterwards, as cell data, voltages on bit lines may be sensed by corresponding page buffers.
For convenience of description, a memory cell connected with an unselected word line is referred to as an unselected memory cell, and a memory cell connected with a selected word line is referred to as a selected memory cell.